The overarching objective of the PROARTIS project is to facilitate a probabilistic approach to timing analysis. The proposed approach will concentrate on proving that pathological timing cases can only arise with negligible probability, instead of struggling to eradicate them, which is arguably not possible and could severely degrade performance. This will be a major turn from previous approaches that seek analyzability by trying to predict with cycle accuracy the state of hardware and software through analysis.
The central hypothesis of PROARTIS is that new advanced hardware/software features enabling truly randomized timing behaviour can be defined for use in critical real-time embedded (CRTE) systems. This paradigm shift will permit probabilistic analysis techniques to be used effectively in arguments of system verification and certification, by demonstrating that the probability of pathological execution times is negligible.
PROARTIS focuses on the probabilistic timing analysis of critical real-time embedded systems
The techniques developed in PROARTIS will enable probabilistic guarantees of timing correctness to be derived. For example, if the reliability requirements placed on a sub-system indicate that the probability of a timing failure (a WCET violation) must be less than 10-9 per hour of operation, then the analysis techniques developed in PROARTIS shall translate this requirement into a probabilistic worst-case execution time guarantee for the sub-system. Probabilistic analysis effectively provides a continuum of worst-case execution times (WCET) for different confidence levels. Thus a sub-system may have a probability of 10-8 per hour of exceeding an execution time of 1.5 ms, and probabilities of 10-9, and 10-10 per hour of exceeding 1.55 ms and 1.59 ms, respectively. The main idea of PROARTIS is that for future CRTE systems, such probabilistic guarantees offer significant advantages over deterministic approaches which attempt to make absolute guarantees, thereby severely limiting the opportunity of use of advanced hardware features and inevitably attaining lesser performance.